TASER Workshop 2021
6 talks · 2021 · indexed by Breach Arc Archive. Links open each talk on YouTube.
Browse with filters →- An overview of security topics within RISC-V, by Helena Handschuh 2021
- Can we solve timing side-channels in the CPU?, Ronan Lashermes, INRIA 2021
- CHERI and CHERI-RISC-V, by Simon Moore, University of Cambridge 2021
- Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs, Barbara Gigerl, 2021
- Current status of RISC-V security mechanisms, Nick Kossifidis, FORTH 2021
- RISC-V cryptography extensions: current status and future plans, Ben Marshall 2021