A High Throughput Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths

Name: A High Throughput Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths
Uploaded: 2016-01-01
Duration: 20 min 25 s
Description: A High Throughput Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths — a 2016 CHES 2016 security conference talk on hardware-firmware, crypto (20:25 min). Watch the full video, indexed free on the Breach Arc Archive.

CHES 2016 · 2016 · 20:25

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A High Throughput Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths — a 2016 CHES 2016 security conference talk on hardware-firmware, crypto (20:25 min). Watch the full video, indexed free on the Breach Arc Archive.

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hardware-firmware crypto

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