jn: Project Vicigol - Reverse-engineering a 28-bit RISC CPU

Name: jn: Project Vicigol - Reverse-engineering a 28-bit RISC CPU
Duration: 43 min 10 s
Description: jn: Project Vicigol - Reverse-engineering a 28-bit RISC CPU — a Chaos Computer Club (media.ccc.de) security conference talk on reverse-engineering, hardware-firmware (43:10 min). Watch the full video, indexed free on the Breach Arc Archive.

Chaos Computer Club (media.ccc.de) · 43:10

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jn: Project Vicigol - Reverse-engineering a 28-bit RISC CPU — a Chaos Computer Club (media.ccc.de) security conference talk on reverse-engineering, hardware-firmware (43:10 min). Watch the full video, indexed free on the Breach Arc Archive.

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reverse-engineering hardware-firmware

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